Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits

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http://eprints.org/relation/isVersionOf http://etheses.bham.ac.uk/id/document/981 http://eprints.org/relation/isVolatileVersionOf http://etheses.bham.ac.uk/id/document/981 http://eprints.org/relation/isIndexCodesVersionOf http://etheses.bham.ac.uk/id/document/981 archive 4031 disk0/00/00/04/07 2009-12-03 09:47:53 2019-01-23 09:52:06 2011-07-19 16:16:58 thesis show 0 Abu Issa Abdallatif S Quigley Steven Francis University of Birmingham Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits unpub TK 10col_ephy Built-In Self-Test (BIST), Linear Feedback Shift Register (LFSR), Low Power Design, Digital Circuits, Design for Test Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to addresses these challenges during test. The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The proposed BS-LFSR is then extended for use in test-per-scan BIST. The results obtained while scanning in test vectors show up to 60% reduction in average power consumption. The BS-LFSR is then extended further to act as a multi-degree smoother for test patterns generated by conventional LFSRs before applying them to the CUT. Experimental results show up to 55% reduction in average power. Another technique that aims to reduce peak power in scan-based BIST is presented. The new technique uses a two-phase scan-chain ordering algorithm to reduce average and peak power in scan and capture cycles. Experimental results show up to 65% and 55% reduction in average and peak power, respectively. Finally, a technique that aims to significantly increase the fault coverage in test-per-scan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques. 2009-12 2009-09 graduation eng author This unpublished thesis/dissertation is copyright of the author and/or third parties. The intellectual property rights of the author or third parties in respect of this work are as defined by The Copyright Designs and Patents Act 1988 or as modified by any successor legislation. Any use made of information contained in this thesis/dissertation must be in accordance with that legislation and must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the permission of the copyright holder. ubira@lists.bham.ac.uk public 143 University of Birmingham School of Engineering, Department of Electronic, Electrical and Systems Engineering d_ph royal_society 2009-12 graduation