Solution of partial differential equations using reconfigurable computing

Hu, Jing (2011). Solution of partial differential equations using reconfigurable computing. University of Birmingham. Ph.D.

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Abstract

This research undergone is an inter-disciplinary project with the Civil Engineering Department, which focuses on acceleration of the numerical solutions of Partial differential equations (PDEs) describing continuous solid bodies (e.g. a dam or an aircraft wing). Numerical techniques for solutions to PDEs are generally computationally demanding and data intensive. One approach to acceleration of their numerical solutions is to use FPGA based reconfigurable computing boards. The aim of this research is to investigate the features of various algorithms for the numerical solution of Laplace’s equation (the targeted PDE problem) in order to establish how well they can be mapped onto reconfigurable hardware accelerators. Finite difference methods and finite element methods are used to solve the PDE and they are characterized in terms of their operation count, sequential and parallel content, communication requirements and amenability to domain decomposition. These are then matched to abstract models of the capabilities of FPGA-based reconfigurable computing platforms. The performance of different algorithms is compared and discussed. The resulting hardware design will be suitable for platforms ranging from single board add-ins for general PCs to reconfigurable supercomputers such as the Cray XD1. However, the principal aim in this research has been to seek methods that perform well on low-cost platforms. In this thesis, several algorithms of solving the PDE are implemented on FPGA-based reconfigurable computing systems. Domain decomposition is used to take advantage of the embedded memory within the FPGA, which is used as a cache to store the data for the current sub-domain in order to eliminate communication and synchronization delays between the sub-domains and to support a very large number of parallel pipelines. Using Fourier decomposition, the 32bit floating-point hardware/software design can achieve a speed-up of 38 for 3-D 256x256x256 finite difference method on a single FPGA board (based on a Virtex2V6000 FPGA) compared to a software solution implemented in the same algorithm on a 2.4 GHz Pentium 4 PC which supports SSE2. The 32 bit floating-point hardware-software coprocessor for the 3D tetrahedral finite element problem with 48,000 elements using the preconditioned conjugate gradient method can achieve a speed-up of 40 for a single FPGA board (based on a Virtex4VLX160 FPGA) compared to a software solution.

Type of Work:

Thesis (Doctorates > Ph.D.)

Award Type:

Doctorates > Ph.D.

Supervisor(s):